The use of a Universal Serial Bus (USB) for coupling a peripheral device to a host computer/controller has become well known. Moreover, the maximum transmission rate of the USB is continually increasing. For example, while the USB 1.0 standard provided a transmission rate of 12 Mb/s, the USB 2.0 standard provides for a transmission rate of 480 Mb/s (a full 40×faster). As the speed of data transmission continually increases, it is becoming increasing important and difficult to accurately test the components responsible for transmitting and receiving the data (i.e., the data transceiver forming the USB interface). Moreover, due to the high speed of operation, it is typically necessary to test the transceiver under normal operating conditions in order to accurately evaluate the functionality of the transceiver.
In order to accomplish such testing and evaluation, typically, such high-speed circuits incorporate some form of a built-in test circuit, which is capable of performing a self-test on the transceiver while simulating normal operation conditions. Such built-in test circuits function to generate a test pattern which is input and routed through the transmitter portion of the transceiver operating at the normal operational data rate. The data routed through the transmitter portion is then routed to the receiver portion of the transceiver, and upon being processed by the receiver portion, the received data is compared with the known test pattern input into the transmitter portion. If the transceiver is operating correctly, the received data will match the test pattern input into the transmitter portion.
U.S. Pat. No. 6,201,829 illustrates a typical built-in test circuit utilized for testing the functionality of transceiver under normal operating conditions. Referring to FIG. 5 of the '829 patent, the self-test circuit includes a built-in self test (BIST) circuit 62, which functions to generate a test pattern. This test pattern is then coupled to the transmitter section formed by input latch 50, serializer 52 and output buffer 54. The output of buffer 54 is also coupled to the receiver section via multiplexer 55. The receiver section includes sampler 56, deserializer 58, output driver 60 and a BIST signal analyzer 61.
In order to conduct the self-test, a self-test signal is activated. This signal functions to control the multiplexer 35 such that the multiplexer selects the output of the BIST 62 as the input data to the transmitter section. The signal also controls multiplexer 55 such that the multiplexer selects the output of buffer 54 as the input data to the receiver section. When operating in the self-test mode, upon receipt of the incoming data, the BIST signal analyzer 61 compares the incoming data to determine if an error has occurred. It is noted that the BIST signal analyzer contains a data pattern identical to the one generated by the BIST circuit 62 so as to allow the BIST signal analyzer to perform the necessary comparison.
Notwithstanding the ability of known BIST circuits to test transceivers under normal operating conditions, the known prior art designs suffer from the following problems. First, as the data transmission speeds become faster and faster, the protocols associated with the standards governing the transmission of data are becoming exceedingly complex. Accordingly, it is often necessary to be able to vary the input test data in order to allow for a complete test to be performed on the device. Moreover, it may be necessary to vary the input test data during the testing process in order to isolate and identify a given component failure. Known BIST circuits do not provide any means for controlling and/or varying the input data during the testing process.
Furthermore, known BIST circuits do not allow for separate control of the transmitter section and the receiver section during the self-test process. For example, as shown in the '829 patent, selection of the self-test mode automatically controls both the transmitter section and the receiver section to the self-test mode of operation. However, as explained in more detail below, it is sometimes necessary to isolate the operation of the transmitter section and the receiver section during self-test operations so as to allow for detection of errors in, for example, the transmitter section.
Accordingly, there is exists a need for a built-in self-test (BIST) circuit which allows for external data to be input as the test data during the testing sequence, and which allows for isolation of the transmitter section and receiver section during the self-test operation.